1. Field of the Invention
This invention relates generally to ferroelectric memory devices with non-volatile data storability using ferroelectric capacitors and, more particularly, to a nonvolatile ferroelectric memory device having a cell block configured from a serial combination of multiple unit cells, each of which is made up of a parallel connection of one ferroelectric capacitor and one cell transistor. The invention also relates to a data read control method of this memory device.
2. Description of Related Art
Ferroelectric random access memory devices store data nonvolatilely in a way depending upon the magnitude of a remnant polarization of a ferroelectric capacitor. Prior known ferroelectric memory chips are designed in general so that a memory cell consists of a serial combination of a ferroelectric capacitor and a cell transistor in a similar way to that of dynamic random access memories (DRAMs). However, unlike the DRAMs, ferroelectric memories are nonvolatile memories of the type storing data based on the remnant polarization amount. Thus, it becomes necessary to drive a plate line in order to read signal charge onto a bit line. For the very reason, in prior art ferroelectric memories, plate-line driving circuitry must require consumption of a relatively large chip area.
In contrast, an advanced ferroelectric memory cell array scheme capable of reducing the on-chip area of plate-line drive circuitry has been proposed by Takashima et al. This scheme is the one that arranges a unit cell by connecting both ends of a ferroelectric capacitor (C) to the source and drain of a cell transistor (T) respectively and then serially connecting together a plurality of unit cells each having such TC parallel connection to thereby make up a cell block, as disclosed in D, Takashima et al., “High-Density Chain Ferroelectric Random Access Memory (CFRAM),” in Proc. VLSI Symp. June 1997, pp. 83-84. With this type of ferroelectric memory chips, also known au “TC parallel unit-cell series-connection” type ferroelectric memories, it is possible to permit a number, e.g. eight (8), of unit cells to commonly have or “share” a plate-line drive circuit, which in turn makes it possible to mount an increased number of cell arrays on a chip at higher integration densities,